The present invention relates to the art of electronic packaging, and more specifically to assemblies incorporating semiconductor chips and to methods and components useful in making such assemblies.
Modern electronic devices utilize semiconductor chips, commonly referred to as xe2x80x9cintegrated circuitsxe2x80x9d which incorporate numerous electronic elements. These chips are mounted on substrates which physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be a part of a discrete chip package used to hold a single chip and equipped with terminals for interconnection to external circuit elements. Such substrates may be secured to an eternal circuit board or chassis. Alternatively, in a so-called xe2x80x9chybrid circuitxe2x80x9d one or more chips are mounted directly to a substrate forming a circuit panel arranged to interconnect the chips and the other circuit elements mounted to the substrate. In either case, the chip must be securely held on the substrate and must be provided with reliable electrical interconnection to the substrate. The interconnection between the chip itself and its supporting substrate is commonly referred to as xe2x80x9cfirst levelxe2x80x9d assembly or chip interconnection, as distinguished from the interconnection between the substrate and the larger elements of the circuit, commonly referred to as a xe2x80x9csecond levelxe2x80x9d interconnection.
The structures utilized to provide the first level connection between the chip and the substrate must accommodate all of the required electrical interconnections to the chip. The number of connections to external circuit elements, commonly referred to as xe2x80x9cinput-outputxe2x80x9d or xe2x80x9cI/Oxe2x80x9d connections, is determined by the structure and function of the chip. Advanced chips capable of performing numerous functions may require substantial numbers of I/O connections.
The size of the chip and substrate assembly is a major concern. The size of each such assembly influences the size of the overall electronic device. More compact assemblies, with smaller distances between chips provide smaller signal transmission delays and hence permit faster operation of the device.
First level interconnection structures connecting a chip to a substrate ordinarily are subject to substantial strain caused by thermal cycling as temperatures within the device change during operation. The electrical power dissipated within the chip tends to heat the chip and substrate, so that the temperatures of the chip and substrate rise each time the device is turned on and fall each time the device is turned off. As the chip and the substrate ordinarily are formed from different materials having different coefficients of thermal expansion, the chip and substrate ordinarily expand and contract by different amounts. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the substrate as the temperature of the chip and substrate changes. This relative movement deforms the electrical interconnections between the chip and substrate and places then under mechanical stress. These stresses are applied repeatedly with repeated operation of the device, and can cause breakage of the electrical interconnections. Thermal cycling stresses may occur even where the chip and substrate are formed from like materials having similar coefficients of thermal expansion, because the temperature of the chip may increase more rapidly than the temperature of the substrate when power is first applied to the chip.
The cost of the chip and substrate assembly is also a major concern. All these concerns, taken together, present a formidable engineering challenge. Various attempts have been made heretofore to provide primary interconnection structures and methods to meet these concerns, but none of these is truly satisfactory in every respect. At present, the most widely utilized primary interconnection methods are wire bonding, tape automated bonding or xe2x80x9cTABxe2x80x9d and flip-chip bonding.
In wire bonding, the substrate has a top surface with a plurality of electrically conductive contact pads or lands disposed in a ring-like pattern. The chip is secured to the top surface of the substrate at the center of the ring-like pattern, so that the chip is surrounded by the contact pads on the substrate. The chip is mounted in a face-up disposition, with the back surface of the chip confronting the top surface of the substrate and with the front surface of the chip facing upwardly, away from the substrate, so that electrical contacts on the front surface are exposed. Fine wires are connected between the contacts on the front face of the chip and the contact pads on the top surface of the substrate. These wires extend outwardly from the chip to the surrounding contact pads on the substrate. In the wire bonded assemblies, the area of the substrate occupied by the chip, the wires and the contact pads of the substrate is substantially greater than the surface area of the chip itself.
In tape automated bonding, a polymer tape is provided with thin layers of metallic material forming conductors on a first surface of the tape. These conductors are arranged generally in a ring-like pattern and extend generally radially, towards and away from the center of the ring-like-pattern. The chip is placed on the tape in a face down arrangement, with contacts on the front surface of the chip confronting the conductors on the first surface of the tape. The contacts on the chip are bonded to the conductors on the tape. Ordinarily, numerous patterns of conductors are arranged along the length of the tape and one chip is bonded to each of these individual patterns, so that the chips, once bonded to the tape, can be advanced through successive work stations by advancing the tape. After each chip is bonded to the metallic conductors constituting one pattern, the chip and the immediately adjacent portions of the pattern are encapsulated and the outermost portions of the metallic conductors are secured to additional leads and to the ultimate substrate. Tape automated bonding can provide the assembly with good resistance to thermal stresses, because the thin metallic leads on the tape surface are quite flexible, and will bend readily upon expansion of the chip without imposing significant stresses at the juncture between the lead and the contact on the chip. However, because the leads utilized in tape automated bonding extend outwardly in a radial, xe2x80x9cfan outxe2x80x9d pattern from the chip, the assembly is much larger than the chip itself.
In flip-chip bonding, contacts on the front surface of the chip are provided with bumps of solder. The substrate has contact pads arranged in an array corresponding to the array of contacts on the chip. The chip, with the solder bumps, is inverted so that its front surface faces toward the top surface of the substrate, with each contact and solder bump on the chip being positioned on the appropriate contact pad of the substrate. The assembly is then heated so as to liquify the solder and bond each contact on the chip to the confronting contact pad of the substrate. Because the flip-chip arrangement does not require leads arranged in a fan-out pattern, it provides a compact assembly. The area of the substrate occupied by the contact pads is approximately the same size as the chip itself. Moreover, the flip-chip bonding approach is not limited to contacts on the periphery of the chip. Rather, the contacts on the chip may be arranged in a so-called xe2x80x9carea arrayxe2x80x9d covering substantially the entire front face of the chip. Flip-chip bonding therefore is well suited to use with chips having large numbers of I/O contacts. However, assemblies made by flip-chip bonding are quite susceptible to thermal stresses. The solder interconnections are relatively inflexible, and may be subjected to very high stress upon differential expansion of the chip and substrate. These difficulties are particularly pronounced with relatively large chips. Moreover, it is difficult to test and operate or xe2x80x9cburn-inxe2x80x9d chips having an area array of contacts before attaching the chip to the substrate. Additionally, flip-chip bonding ordinarily requires that the contacts on the chip be arranged in an area array to provide adequate spacing for the solder bumps. Flip-chip bonding normally cannot be applied to chips originally designed for wire bonding or tape automated bonding, and having rows of closely spaced contacts on the periphery of the chip.
One aspect of the present invention provides a semiconductor chip assembly. An assembly according to this aspect of the invention typically includes a semiconductor chip having a plurality of surfaces and having contacts on at least one of said surfaces. The assembly further includes a sheetlike, preferably flexible, element having terminals thereon, the terminals being electrically connected to the contacts on the chip. Assemblies according to this aspect of the invention are characterized in that the sheetlike element and at least some of said terminals overly one surface of said chip, said terminals are movable with respect to said chip and in that resilient means for permitting displacement of the terminals toward the chip, but resisting such displacement are provided. Most preferably, a compliant layer is disposed between said terminals and said chip so that said compliant layer will be compressed upon movement of said terminals toward said chip.
The complaint layer may be incorporated in the sheetlike element, or formed separately therefrom. The contacts typically are disposed on the front or top surface of the chip. The sheetlike element and terminals may overlie said front surface of the chip. Alternatively, the sheetlike element and said terminals may overlie the rear, or bottom surface of said chip. The terminals on the sheetlike element can be connected to contact pads on a substrate, as by solder bonding. Because the terminals, and hence the contact pads on the substrate overlie the chip front or back surface, the assembly is compact. The ability of the terminals to move with respect to the chip in directions parallel to the chip surfaces provides compensation for differential thermal expansion of the chip and substrate.
The ability to accumulate movement of the terminals towards the face of the chip greatly facilitates temporary engagement of the terminals by test equipment and hence facilitates testing and xe2x80x9cburn-inxe2x80x9d of the assembly before the same is mounted to a substrate. According to a further aspect of the present invention, the compliant layer includes masses of compliant material interspersed with holes. Desirably, each such mass is aligned with one of the terminals.
A further aspect of the invention provides a method of making a semiconductor chip assembly including the step of assembling a flexible, sheetlike element having terminals thereon to a semiconductor chip and connecting terminals on said sheetlike element to contacts on said chip. Methods according to this aspect of the invention desirably are characterized in that the assembling step is conducted so that said terminals on said sheetlike element overlie a surface of the chip and in that a compliant layer is disposed between said chip and said terminals. Most preferably, these methods are further characterized by the step of testing the chip by establishing temporary electrical contact between a plurality of test probes and said terminals and utilizing said temporary electrical contact to actuate said chip. The compliant layer permits displacement of at least some of said central terminals toward said chip during the step of establishing temporary electrical contact. The step of establishing temporary electrical contact preferably includes the step of simultaneously establishing temporary contact between a plurality of terminals and a plurality of test probes rigidly connected to a test fixture.
Further aspects of the invention provide components for assembly to a semiconductor chip including a flexible sheetlike element having terminals thereon, characterized by a compliant layer underlying said terminals. The compliant layer preferably includes masses of a low modulus material and holes interspersed with said masses of low modulus material, said masses of said low modulus material being aligned with said terminals, said holes in said compliant layer being out of alignment with said terminals.
A chip assembly according to a further aspect of the invention includes a semiconductor chip having a front surface with a plurality of contacts disposed in a pattern on the front surface. The pattern of contacts on the front surface encompasses an area, referred to herein as the xe2x80x9ccontact pattern area,xe2x80x9d on the front surface. The chip assembly according to this aspect of the invention also includes a sheetlike dielectric element, referred to herein as xe2x80x9cinterposerxe2x80x9d, overlying the front surface of the chip. The interposer has a first surface facing toward the chip and a second surface facing away from the chip. An area of the interposer overlies the contact pattern area of the chip. The interposer has apertures extending through it, from the first surface to the second surface. The interposer also has a plurality of electrically conductive terminals disposed in a pattern on the second surface of the interposer. At least some of these terminals, and preferably most or all of these terminals, are disposed within the area of the interposer overlying the contact pattern area on the chip. Each such terminal is associated with one contact on the chip.
The assembly also includes flexible, electrically conductive leads. The leads preferably extend through the apertures in the interposer. Each such lead has a contact end connected to the assembly associated contact of the chip and a terminal end connected to the associated terminal on the second surface of the interposer. The leads and the interposer are constructed and arranged so that the contact ends of the leads are moveable relative to the terminals at least to the extent required to compensate for differential thermal expansion of components. The leads desirably are flexible to permit such movement. Most preferably, the interposer itself is flexible so as to facilitate such movement. The assembly according to this aspect of the invention optionally may include a compliant layer as discussed above.
The assembly incorporating the chip, interposer, terminals and leads may be incorporated in a larger assembly including a substrate having a top surface facing toward the second surface of the interposer.
Preferred chip assemblies according to this aspect of the present invention are compact and may be utilized with chips having large numbers of input-output connections. The terminals on the interposer, and the corresponding contact pads on the substrate, desirably are disposed in areas substantially the same size as the contact pattern area on the chip itself.
The flexible leads may be formed integrally with the terminals on the interposer, or else may be separately formed fine wires. The leads desirably are curved to provide increased flexibility. The interposer desirably is a thin, flexible sheet of a polymeric material such as polymide, a fluoropolymer, a thermoplastic polymer or an elastomer. In this arrangement, flexing of the interposer facilitates movement of the contact ends of the leads relative to the terminals and thus contributes to the ability of the assembly to withstand thermal cycling. The assembly may also include a compliant dielectric encapsulant having a low elastic modulus, such as an elastomeric encapsulant, covering the flexible leads in whole or in part. The encapsulant may be provided in the form of a layer, with holes in the encapsulant layer aligned with the terminals on the second surface of the interposer. The bonds between the terminals and the contact pads of the substrate extend through these holes. The encapsulant protects the relatively delicate leads during handling and during service, but does not prevent flexing of the leads or the absorption by the leads of relative motion of the chip and substrate during thermal expansion.
A chip assembly according to yet another aspect of the present invention incorporates a chip having a front surface including a central region and a peripheral region surrounding the central region, the chip having a plurality of peripheral contacts disposed in the peripheral region of the front surface. The assembly preferably further includes a sheet-like dielectric interposer overlying the central region of the chip front surface. The interposer has a first surface facing downwardly toward the chip and a second surface facing upwardly, away from the chip. The interposer also has edges disposed inwardly of the peripheral contacts. For example, the interposer may overly only the central portion of the chip front surface. A plurality of central terminals are disposed on the interposer and overly the central region of the chip front surface. The assembly preferably also includes a plurality of peripheral contact leads connecting at least some of the peripheral contacts on the chip with at least some of the central terminals on the interposer. Each such peripheral contact lead thus has a central terminal and overlying the interposer and connected to one of the central terminals and a contact and projecting outwardly beyond one of the edges of the interposer and connected to one of the peripheral contacts. Each peripheral contact lead extends inwardly from one of the peripheral contacts to one of the central terminals on the interposer. The peripheral contact leads and preferably the interposer as well are at least partially flexible so that the central terminals are movable with respect to peripheral contacts to accommodate movement caused by differential thermal expansion. Here again, the assembly may optionally include a compliant layer as discussed above. Desirably, the peripheral contact leads include bent portions.
The peripheral contact leads and central terminals provide a xe2x80x9cfan-inxe2x80x9d arrangement in which the terminals on the interposer are disposed inside the region bounded by the peripheral contacts on the chip. Typically, the peripheral contacts on the chip are disposed in one or two rows along each edge of the chip, in a generally rectangular pattern, so that the contacts on the chip are close to one another. By contrast, the terminals on the interposer may be substantially evenly disposed over the second surface of the interposer. The central terminals may be disposed in a so-called xe2x80x9carea arrayxe2x80x9d. Accordingly, the distance between adjacent terminals may be substantially greater than the distance between adjacent contacts on the chip. The distances between adjacent terminals on the interposer may be large enough to accommodate solder bonding and similar processes which require substantial distances between adjacent bonds.
Some or all of the peripheral contact leads may have outward extensions projecting outwardly beyond the peripheral contacts of the chip. The assembly may include securement means for holding these outward extensions. For example, one or more securement elements may be disposed outwardly of the peripheral contacts, and each such securement element may be physically connected to a plurality of the outward extensions on the peripheral contact leads. Each such securement element may be a generally planar strip of dielectric material having an inboard edge extending generally parallel to one of the edges of the interposer so that each pair of parallel edges define an elongated slot between each such securement element and the interposer, and each peripheral contact lead may extend across one of these slots. In this arrangement, the peripheral contacts of the chip may be disposed in alignment with the slots between the securement elements and the interposer. The securement element may be physically connected to the interposer, as by bridge elements extending between the securement elements and the interposer at spaced-apart locations around the periphery of the chip front surface. The securement elements, bridge elements and interposer may be formed integrally with one another as a single, sheet-like unit. The securement elements provide physical reinforcement to the peripheral contact leads during the manufacturing operations and in service. Additional terminals, referred to herein as xe2x80x9coutsidexe2x80x9d terminals, may be disposed on the securement elements, and may be connected to some of the peripheral contacts on the chip by outside terminal leads extending across the slots, the inboard ends of the outside terminal leads being secured to the interposer so that the slot and interposer cooperatively provide reinforcement, to the outside terminal leads as well.
These assemblies may be made by methods which include the step of assembling a sheet-like dielectric interposer to the chip so that the interposer overlies the central region of the chip front surface, the outboard edges of the interposer being disposed inwardly of the peripheral contacts on the chip. When the dielectric interposer is disposed on the chip, a first surface of the interposer faces downwardly toward the chip and a second surface of the interposer faces upwardly away from the chip, and a plurality of central terminals on the interposer overly the central region of the chip front surface. The method further includes the step of connecting a plurality of peripheral contact leads between at least some of the peripheral contacts of the chip and at least some of the central terminals on the interposer, so that each such peripheral contact lead extends inwardly from one of the peripheral contacts on the chip to one of the central terminals on the interposer. The method may further include the step of assembling a substrate having a plurality of contact pads to be assembled with the interposer and chip and connecting each of the central terminals on the interposer to one of the contact pads on the substrate.
The interposer may have prefabricated leads mounted thereon and connected to the central terminals before the interposer is assembled to the chip. In this case, the prefabricated contact leads are positioned on the chip when the interposer is assembled to the chip. Such prefabricated contact leads may be electrically connected to the contacts of the chip by thermocompression bonding or similar processes. Alternatively, the peripheral contact leads may be formed after the interposer is applied to the chip, as in a wire-bonding step in which a fine wire is dispensed and formed into a lead connecting the contact and terminal. Preferably, securement elements are provided as discussed above with reference to the chip assembly, and the securement elements are connected to the interposer before the interposer is placed on the chip. In this case, the securement elements may support the prefabricated leads during the step of placing the interposer on the chip.
A semiconductor chip assembly in accordance with yet another aspect of the invention includes a semiconductor chip having oppositely facing front and rear surfaces with edges extending between these surfaces, the chip having contacts on the front surface. The assembly further includes a generally sheet-like element referred to herein as a xe2x80x9cbacking elementxe2x80x9d underlying the chip, the backing element having a top surface facing toward the chip and a bottom surface facing away from the chip. A central region of the backing element is aligned with the chip. The backing element is provided with terminals. At least some, and preferably all of the terminals on the backing element are disposed in the central region, so that the terminals underlie the bottom surface of the chip. The assembly in accordance with this aspect of the present invention further includes electrically conductive leads interconnecting the contacts on the chip front surface with the terminals on the backing element, these leads extending alongside the edges of the chip. Preferably, the backing element and the leads are flexible so that the terminals on the backing element are moveable with respect to the chip. Thus, the terminals desirably are moveable with respect to the contacts on the front surface of the chip in directions parallel to the plane of the chip top and bottom surfaces. The backing element and leads provide for connection to the chip at the back surface, so that the chip can be mounted in face-up disposition on a substrate. However, because the terminals on the backing element are disposed in the central region and aligned with the chip itself, the connections to the substrate can be made in the area beneath the chip. Therefore, the assembly need not be substantially larger than the chip itself.
The ability to accommodate relative movement between the chip and the terminals on the backing element allows the assembly to accommodate differential thermal expansion between the chip and substrate. Desirably, the terminals on the backing elements are also moveable relative to the chip in directions towards the bottom surface of the chip as discussed above, and the assembly may include resilient means for permitting movement of the terminals towards the bottom surface but resisting such movement. For example, the assembly may incorporate a layer of a compliant material disposed between the chip rear surface and the terminals.
Most desirably, the assembly includes at least one generally sheet-like flap connected to the backing element. Each such flap extends upwardly, towards the front surface of the chip and away from the backing element alongside one edge of the chip. Each of the aforementioned leads desirably includes a flap portion extending along one of these flaps. The flaps may be formed integrally with the backing element. Desirably, both of the flaps and the backing element include electrically conductive layers and a dielectric layer disposed between the electrically conductive layers and the leads so as to provide a controlled impedance in the leads. Assemblies of this type are especially well suited to use with chips having contacts arranged in rows adjacent the periphery of the chip front surface peripherate. Desirably, each flap extends to the vicinity of at least one row of contacts. The flap portions of the leads on each such flap are connected to the adjacent row of contacts. Such connection may be made, for instance, by wire bonding or by direct connections between the flap portions of the leads and the contacts on the chip. Even where wire bonding is employed, however, the wires extending between the chip contacts and the flap portions of the leads are short. Such short wire bonds can be readily applied and have relatively low inductance.
Most preferably, the chip assembly includes one or more support elements disposed between the flaps and the edges of the chip. The support elements may cooperatively constitute a ring or box surrounding the chip. The box may also incorporate a floor element disposed beneath the rear surface of the chip, between the rear surface and the backing element. Where the assembly includes a floor element underlying the chip rear surface, the compliant layer may be disposed between the floor element and the terminals, as, for example, between the floor element and the backing element. These arrangements provide for mechanical support of the flaps and protection of the interconnections. Further protection may be afforded by encapsulating the assembly.
Further aspects of the invention provide components incorporating subassemblies of the backing element, leads and support element. Preferably, these components include support elements defining a box, and include flaps integral with the backing element extending upwardly along the sides of the box. The conductors extending along the flaps are prepositioned adjacent the top edges of the box walls. In manufacture of the assembly, the chip may be placed within the box and the conductors may be joined to the chip terminals.
Assemblies as discussed above may be incorporated in a larger assembly with a substrate having contact pads, the contact pads of the substrate being aligned with the terminals on the backing element and connected thereto. Such connection may be made, for example, by masses of electrically conductive bonding material disposed between the terminals and the contact pads of the substrate.
A further aspect of the present invention provides a circuit assembly including a plurality of chip assemblies, each including an interposer and a backing element as discussed above. According to this aspect of the invention, the chip assemblies may be arranged in a stack, one on top of the other, such that each chip assembly other than the bottom-most chip assembly overlies another, immediately subjacent chip assembly. The bottom surface of the backing element in each such overlying chip assembly faces the second surface of the interposer of the immediate subjacent chip assembly. Most preferably, at least some of the inside terminals on the backing element of each such overlying chip assembly are connected to the central terminals on the interposer of the immediately subjacent chip assembly, so that the chips of the various chip assemblies are electrically connected to one another.
Further aspects, features and advantages of the present invention will be more readily apparent from the detailed description of the preferred embodiments set forth below, taken in conjunction with the accompanying drawings.